News for hackers. Stuff that matters.
Re:RISC-V is succeeding by imtringued on Wednesday March 02, 2022 @07:02AM (#30526377)
I thought that at first but the truth is that x86 and ARM are stuck in a certain mindset, their instruction sets are so complicated it is impossible to mix compressed and uncompressed instructions. Once you consider compression then RISC-V is on average slightly denser than x86. Compression will be everywhere by default.

The only really janky part is the fusion of more than 3 instructions. Now that is insane. However, it is like energy storage for renewables. Once you have an electric grid that can store days worth of energy that's actually extremely amazing. The old way of doing things will be viewed as something cavemen or barbarians did. If macro op fusion scales beyond 3 instructions then RISC V will easily beat other architectures because 2 is the limit for every other architecture.

Re:RISC-V is succeeding by snvzz on Tuesday March 08, 2022 @02:45PM (#30605576)
>Once you consider compression then RISC-V is on average slightly denser than x86.

A note for those not following: RISC-V as in RV64GC. x86 as in 32bit x86.

64bit x86 aka x86-64 aka amd64 is dramatically worse in code density.