Not really, students have been designing RISC cores as long as RISC has been around. It's a standard exercise.

RISCV does make it a bit easier and gives you a clean ISA but it hasn't really had that much of an influence due to its own design i.e. it's caused people to herd around it so there's lots of tutorials and work to borrow floating around.

Having a relatively sophisticated core you can take off the shelf and modify for your own research can be incredibly useful in academia, I would have really liked that when I was doing my thesis. For large companies too who might want particular new instructions or sets of features that are best suited to their own use cases.

SPARC has been open source since 2005, complete with high quality implementation released in 2006. 64-bit, 8 cores, 32 hyperthreads, rising to 64 by 2007. Simulator also provided.

SPARC was able to run Linux and Solaris, and used by Sun in their servers that powered much of the commercial internet in late 90s and early 2000s (before x86 Linux took over).

There have been a few others since then. So relatively sophisticated open source cores for study and modification have been around for many years by now.

It looks to me like the difference with RISC-V is that a larger community has formed around it due to smart organisation and the timing being right, rather than availability.

This is because the underlying CAD tooling has gotten much smarter and easier to use. It's not because of anything RISCV did in particular.

This toolchain enables going from knowing nothing to a core in one class. One doesn't even need to enroll in the class to follow along.

See: https://ocw.mit.edu/courses/electrical-engineering-and-compu...

Surely it is because of the open source ecosystem, especially open-source tooling, reaching a critical mass?

From article: “The open-source community developed key tools that are crucial to make RISC-V-based processors ubiquitous, such as chip technology process design kits, design verification suites, implementation tools, and more”

Closed source tooling was available and “smart”, but licensing, cost, and inflexibility were significant roadblocks. Disclaimer: I don’t work in the industry.

I think to really have the conversation we would have to define the terms. Much of the original CAD tooling was open source because it was written at Universities.

Things like: is it enough for one to make any core or does one have to make the "best" core? If it just has to exist that was pretty much always possible. Definitely not the lowest friction way to go. But possible.

For example here is basic MIPS core originally written in 2003, from chapter 1 of a common VLSI textbook: http://pages.hmc.edu/harris/cmosvlsi/4e/code.html

It's just over 400 lines of verilog and super easy to follow. The tooling changes that happened in the 90s made that possible.

I experimented making cores that were taped-out in my University, as an undergraduate, in the late 90s. It didn't cost my University even close to 9 figures. It was definitely a lot harder than now but the designs were also a lot more modest. Things, essentially untrained, students can do now would've been unthinkable then.

Stands to reason then that they are not designing in the same sense, but configuring and customizing. People have been doing that for a while now on FPGA, or in hardware with 8080, and it's hardly anybody's kids. What's so "amazing" about it?

Dumb cores are a commodity now, which progressed in horsepower from their ca. 60 years old ancestors. I.e. the core is hardly innovative, so what is so amazing about it, technically?