Not really. You can't reliably make large features with a small process node, and because the smaller processes are dramatically slower and more expensive and have lower yield, unless you can counter all that with more dies per wafer you end up with a whole lot of defective parts at enormous expense. The bigger the die, the higher the chance of a defect landing on it, and making it useless. Also small feature processes have much lower capacity than larger feature processes, so even if you were able to switch there wouldn't be nearly enough wafer capacity. The fact it's 4-5 orders of magnitude more expensive doesn't help either.

> You can't reliably make large features with a small process node

Why is that?

Because (very very roughly) the way you make small features is by scaling down your projection area to a tiny size and then stepping it across the wafer. Your projection area boundaries are where errors are most likely, and the bigger your features the more such boundaries they cross. The details are quite involved, but this is the general problem.

But then the errors are only along the boundaries of a very large feature, which was originally designed for a less precise process.

Also, you could use the design files from before any compensation you apply (to compensate for lithography errors), and use those files to derive a new compensation.

No, the errors are inside the feature itself, since it doesn't fit on a single mask. You can't reuse design files on a new process. Everything will be wrong. You have different material properties, different gate capacitances, different parasitics. No matter what you do, you have to redesign to move to a new node. The problem with large features is, even if you do all that work, you still can't reliably make them with the smaller process, and all the benefits of the smaller process (smaller die size, faster switching, higher speeds, shorter interconnects) go away if you use large features.

Aren't the necessary changes relatively "local", though?

That is - timing closure is hard, and it's a "global" problem - if your design fails timing closure, you might have to re-do the entire layout and/or design itself.

However, if you change the gate capacitances, then I would expect that you'd just have to make a lot of small changes in a lot of different (but unrelated) places - which seems like, while tedious, would be immensely parallelizable with the number of engineers, and not risk any complete re-layouts like meeting timing closure would. So, a "redesign" more than a redesign.

What am I missing here?

You're missing that large feature sizes are often used because they need to handle particular voltages and temp ranges. If you change the material properties those characteristics are no longer viable with the original spacings and dimensions, so you get to relayout anyway.

Not a chance, while you can stretch out horizontally to make a 7nm look like a 180nm (conceptually, still has problems in reality), you can't do that vertically. For example, the gate oxide at 7nm works differently than at 180nm.