https://yrashk.com/strata/

I've long thought about how we're influenced by CPU architectures, and importantly, their ISAs.

In a discussion at a meetup, I brought up a topic that interested me for a while: how would an ISA that exposes memory and cache interactions in a more explicit way (because if you think about it, memory is very much I/O), as opposed to being smart and predictive on its own?

An obscure interest, of course. Nevertheless, I wanted to build a quick prototype after that.

What ended up transpiring was a bit larger. A multicore architecture with tiered stores, capabilities, a JIT'd emulator, Verilog RTL with a simulator, a small microkernel OS, UI, JIT Forth, an assembler in its own assembly, a bootstrapping C99 compiler, a few games, a visual debugger, and a few other things.