>This uses an architecture called CHERI (Capability Hardware Enhanced RISC Instructions) developed with researchers at the University of Cambridge (CHERI) architecture that replaces software pointers in the chip.

This has been submitted multiple times over the years [1] including my own submission, but doesn't seems to get much attention / discussion at all on HN.

There is CheriBSD [2] which has support for it.

[1] https://hn.algolia.com/?dateRange=all&page=0&prefix=false&qu...

[2] https://github.com/CTSRD-CHERI/cheribsd