Re:ARM ships ground-breaking Morello secure processor board
by ksec on Saturday January 15, 2022 @11:21PM
(#29953287)
>This uses an architecture called CHERI (Capability Hardware Enhanced RISC Instructions) developed with researchers at the University of Cambridge (CHERI) architecture that replaces software pointers in the chip.
This has been submitted multiple times over the years [1] including my own submission, but doesn't seems to get much attention / discussion at all on HN.
Re:ARM ships ground-breaking Morello secure processor board
by jrtc27 on Saturday January 15, 2022 @08:02PM
(#29952211)
"ARM has developed a prototype architecture based on the Cortex-A core" isn't quite right. Armv8-A (well, Armv8.2-A in this case) is the architecture, Cortex-A is a family of implementations of that architecture. And the Morello implementation (called Rainier) isn't even directly based on a Cortex-A core, it's based on the Neoverse N1, which is itself then derived from the Cortex A76.
This has been submitted multiple times over the years [1] including my own submission, but doesn't seems to get much attention / discussion at all on HN.
There is CheriBSD [2] which has support for it.
[1] https://hn.algolia.com/?dateRange=all&page=0&prefix=false&qu...
[2] https://github.com/CTSRD-CHERI/cheribsd