They're not meant to go together like that -- there's not really an interconnect for it, or any pins on the package to enable something like that. Apple would have to design a new Mx SoC with something like that as an explicit design goal.

I think the problem would be how one chip can access the memory of the other one. The big advantage in the M1xxxx is the unified memory. I don't think the chips have any hardware to support cache coherency and so on spanning more than one chip.

You would have to implement single system image abstraction, if you wanted more than a networked cluster of M1s in a box, in the OS using just software plus virtual memory. You'd use the PCIe as the interconnect. Similar has been done by other vendors for server systems, but it has tradeoffs that would probably not make sense to Apple now.

A more realistic question would be what good hw multisocket SMP support would look like in M1 Max or later chips, as that would be a more logical thing to build if Apple wanted this.

The rumor has long been that the future Mac Pro will use 2-4 of these “M1X” dies in a single package. It remains to be seen how the inter-die interconnect will work / where those IOs are on the M1 Pro/Max die.

The M1 is a system-on-a-chip so AIUI there's a bunch of stuff on there that you wouldn't want two of.

That's not a problem, you just turn off what's redundant. AMD did the same thing with their original Threadripper/EPYC models.

I think the issue is OS management of tasks to prevent cpu 1 from having to access memory of cpu 2.

Apple are already planning multi-die systems, judging by their drivers. So yes. Rumors are they have a SKU with two M1 Max dies.