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Re:XiangShan open-source 64-bit RISC-V processor to rival Ar... by goodpoint on Monday July 05, 2021 @01:50PM (#27740252)
The RISC-V ISA specifically allows for custom extensions.

Unfortunately, the licensing model does require the implementations to be FLOSS. This encourages creating a lot of closed stuff with different and incompatible extensions.

Re:XiangShan open-source 64-bit RISC-V processor to rival Ar... by brucehoult on Tuesday July 06, 2021 @01:12AM (#27744453)
It doesn't matter. As long as they implement the core RV64GC instruction set correctly, standard software will run, and if they implement privileged architecture 1.10 or later correctly then the standard Linux kernel will run.

Vendors are free to use custom extensions to implement the bootloader and SBI. Normal code and even the OS won't see that. They can also use custom extensions in hardware drivers. Even in libc, if they want, though that gives more maintenance work.

Re:XiangShan open-source 64-bit RISC-V processor to rival Ar... by rjsw on Monday July 05, 2021 @02:57PM (#27740860)
Whether RISC-V ISA extensions are allowed or not is unrelated to the problems seen with ARM SoCs putting peripheral devices at different addresses.
Re:XiangShan open-source 64-bit RISC-V processor to rival Ar... by a9h74j on Monday July 05, 2021 @03:35PM (#27741169)
Could a device table [for on-chip peripherals] be put right on chip?
Re:XiangShan open-source 64-bit RISC-V processor to rival Ar... by formerly_proven on Monday July 05, 2021 @03:56PM (#27741314)
Yes, that's a devicetree. Those can be tacked onto the kernel image or dynamically loaded from the chip's firmware (which most likely gets it from the firmware flash).
Re:XiangShan open-source 64-bit RISC-V processor to rival Ar... by goodpoint on Monday July 05, 2021 @05:51PM (#27742162)
Sure, but the question was about diversity explosion in general.