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A comment on Silice: A language for hardcoding Algorithms into FPGA hardware. Parent comment

Re:Silice: A language for hardcoding Algorithms into FPGA ha... by zsmi on Tuesday June 22, 2021 @12:21PM (#27593625)
> how do you generate recursive designs in vhdl?

I understand mapping a recursive algorithm to hardware, and VHDL can definitely do that [1]. (even if it is generally a bad idea) But what is a recursive hardware design? It sounds really interesting.

[1] https://vhdlguru.blogspot.com/2010/04/recursive-functions-in...

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Re:Silice: A language for hardcoding Algorithms into FPGA ha... by anon_tor_12345 on Tuesday June 22, 2021 @02:15PM (#27595131)
actually this is exactly what i was talking about i.e. (as far as i understand it) this is essentially a reduction tree. i called it a recursive hardware design because it synthesizes to indeed i was unaware that you recursively call functions in vhdl. thanks!
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