First, how do you cool such a chip? Sure, you could add a bunch of transistors but the thermal costs per transistor will stay the same. Assuming similar design but adding 20 layers, how would you account for your CPU now consuming 600W?
Second, The tech doesn't exist. The problem we have is that layering chips today is basically growing crystals in a controlled fashion. Defects in lower layers spoil upper layers. Today that's already a problem (CPUs today have ~7 or 8 layers). Can you imagine the problem of 20 or 30 layers?
Who knows, maybe we'll come up with solutions to both problems, but that's a big maybe. My bet is that instead we focus on architecture designs. We revisit old but deemed too expensive concepts like an async CPU.
See 3d nand flash cells, see stacked cache and HBM memory. All the usual characters are working on it. Intel, AMD (TSMC), Samsung.
Cooling is an issue, but there are solutions.
There's a reason memory can generally beat computational cores to smaller node sizes. It's because highly uniform circuits are much easier to manufacture. A lot of problems present in CPU logic cores (such as cross talk) just aren't present to the same extent in NAND cells.
It may be a simple typing problem, but Wikipedia doesn't seem to have it.
No, I think x86 passed 14+ layers at least half a decade ago.
It does not reduce price per transistor because each layer still has to be manufactured the same way
The silicon is not actually the expensive part.
We are not yet close enough to the end to say where it is, so that's out of sight IMHO.
The entire reason cloud service providers are looking at and advertising ARM racks is the power savings from operating them.
We've been reliant on node shrinks to push things further. That hard limit is 0.2nm (silicon atom size) we are at ~2nm gate features.
It remains to be seen if we can get to that 0.2nm size, I honestly don't think we can push much further past the 2nm size (I'd imagine 0.5nm will be the limit).
That, to me, is very much being "in sight".