SiFive Tapes Out First 5nm TSMC 32-bit RISC-V Chip with 7.2 Gbps HBM3

Re:SiFive Tapes Out First 5nm TSMC 32-bit RISC-V Chip with 7... by winter_blue on Friday April 16, 2021 @01:24PM (#26836681)

HBM might be an interesting idea. I would love to see multiple bandwidth levels of memory becoming a norm, with computers a very fast small amount of memory, and a larger set of DRR4 or DRR5. We already have multiple levels of cache, why not having multiple levels of RAM? Operating systems and software would need to accommodate a new reality where NUMA is the norm though. But it’s good that we even have the concept of NUMA, so this is not entirely uncharted/unfamiliar territory.

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Re:SiFive Tapes Out First 5nm TSMC 32-bit RISC-V Chip with 7... by wmf on Friday April 16, 2021 @02:55PM (#26837677)

You would love to see computers become harder to program?

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Re:SiFive Tapes Out First 5nm TSMC 32-bit RISC-V Chip with 7... by makapuf on Friday April 16, 2021 @04:29PM (#26838723)

It canbe nice to have the opportunity to program something harder but faster. Counter example: Itanium, which was too hard to program (compilers) for.

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Re:SiFive Tapes Out First 5nm TSMC 32-bit RISC-V Chip with 7... by sanxiyn on Friday April 16, 2021 @05:20PM (#26839207)

It is kind of ironic that compiler theory has advanced and now we can target Itanium no problem. It was a bit (well, a lot) ahead of its time.

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Re:SiFive Tapes Out First 5nm TSMC 32-bit RISC-V Chip with 7... by winter_blue on Friday April 16, 2021 @05:27PM (#26839253)

I would try to build a new compiler (or a LLVM intermediary processing layer) that does NUMA optimizations.

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