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A comment on SiFive Tapes Out First 5nm TSMC 32-bit RISC-V Chip with 7.2 Gbps HBM3. Parent comment

Re:SiFive Tapes Out First 5nm TSMC 32-bit RISC-V Chip with 7... by winter_blue on Friday April 16, 2021 @05:27PM (#26839253)
I would try to build a new compiler (or a LLVM intermediary processing layer) that does NUMA optimizations.
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