I much prefer VHDL to Verilog. Mostly because you can define your own types in VHDL but can't in standard verilog (SystemVerilog is closer to VHDL in capability). Also because the whole reg thing in Verilog just doesn't seem very ergonomic to me - I have to stop and look things up when coding state machines or similar stateful things in Verilog. In VHDL you've got signals and variables. Signals can have state. Variables are only used inside of processes - much easier to remember for me, anyway (maybe my block has to do with learning VHDL first).

And finally VHDL is strongly typed. Verilog is pretty much C-typed meaning it's pretty weak. About a dozen years ago I worked at an EDA company and one of my tasks was to run our generated HDL code through a popular industry linting tool. There were hundreds linting problems with the Verilog code that needed to be fixed. In the VHDL code there were only a couple of things that needed to be addressed - this was mostly due to VHDL's strong type system preventing many of the problems that showed up on the Verilog side.

I’ve been told Verilog is more predominant in the US and VHDL in the EU. Any idea how that happened?

Yeah, it's very weird that a language developed by the DoD ended up popular in the EU but much less so in the US. I'm not sure why that happened. I did do a stint in Italy about 16 years ago and they preferred VHDL there at that time as well, so it's not exactly a new phenomenon. I did a VHDL project for a US company last year so it's not like it's completely unheard of here. Another way to look at it is that there are fewer people who know VHDL so when you do find places that are doing VHDL projects there's less competition.