Yes it’s physically different. You could use QLC memory as if it were TLC (just ignore a bit), but you’d be reducing your storage capacity and (to the best of my knowledge) not gain any speed. You can’t do it the other way around- you can’t use TLC as if it were QLC, you can’t make an extra bit appear that the memory controller can’t read and the memory cells weren’t designed for. Basically, if the hardware was only designed to store and read three bits of precision, you aren’t going to reliably get four bits out of it. The engineers wouldn’t have wasted that much margin.

I don’t think you would intentionally ever use QLC as if it were TLC. Leaving it in QLC mode means you’re writing half the number of cells for whatever data you’re storing, which is going to be the best way to maximize drive lifespan.

That's what SLC write caching is.

But my understanding is that uses a totally different chip... Which means the controller can't dynamically reallocate memory cells between QLC and SLC - you have a fixed amount of each.

The SLC cache is always an area of MLC/TLC used as SLC, whether the split is hardcoded or dynamic depends on the exact model. Newer models tend to be dynamic.