LLVM Clang 12 Merges Support For x86_64 Microarchitecture Levels

Re:LLVM Clang 12 Merges Support For x86_64 Microarchitecture... by The_rationalist on Sunday November 08, 2020 @02:47PM (#25028361)

It's not a dumb name change, targeting skylale could generate illegal instructions on modern AMD cpus e.g they lacking TSX or SGX. This is about defining the common intersection of both vendors by generation

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Re:LLVM Clang 12 Merges Support For x86_64 Microarchitecture... by jcranmer on Sunday November 08, 2020 @04:04PM (#25029027)

> they lacking TSX or SGX.

Note that the SGX instructions are system only, so the compiler isn't generating them usually. The hardware lock elision instructions in TSX are specifically chosen so that they act as NOPs on processors that don't support TSX.

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Re:LLVM Clang 12 Merges Support For x86_64 Microarchitecture... by my123 on Sunday November 08, 2020 @04:35PM (#25029296)

Hardware lock elision was disabled via a microcode update. (see https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/lin...)

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Re:LLVM Clang 12 Merges Support For x86_64 Microarchitecture... by throwaway2048 on Sunday November 08, 2020 @08:44PM (#25030659)

Not to mention TSX instructions have been broken in one way or another since their introduction, and now have been removed entirely in new intel silicon.

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Re:LLVM Clang 12 Merges Support For x86_64 Microarchitecture... by my123 on Sunday November 08, 2020 @02:51PM (#25028385)

And assuming those are present for a given gen is even dumber sadly.

There are Comet Lake CPUs with no AVX at all: all Pentiums/Celerons.

Every 10th generation Intel CPU onwards, at least on the client side, doesn't support TSX.

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