LLVM Clang 12 Merges Support For x86_64 Microarchitecture Levels

Re:LLVM Clang 12 Merges Support For x86_64 Microarchitecture... by dragontamer on Sunday November 08, 2020 @02:06PM (#25028039)

Its a dumb name change, but this is a dumb name change that should have happened a while ago.

While ARM has ARMv6, v7, v8... Intel has been using specific names: Nehelem, Haswell, and Skylake (not to be confused with Skylake-X).

A numerical naming scheme, of v1 (Core2), v2 (Nehelem), v3 (Haswell), and v4 (Skylake-X) will be easier to remember moving forward.

[ Parent | on HN ]

Re:LLVM Clang 12 Merges Support For x86_64 Microarchitecture... by The_rationalist on Sunday November 08, 2020 @02:47PM (#25028361)

It's not a dumb name change, targeting skylale could generate illegal instructions on modern AMD cpus e.g they lacking TSX or SGX. This is about defining the common intersection of both vendors by generation

[ Parent | on HN ]

Re:LLVM Clang 12 Merges Support For x86_64 Microarchitecture... by jcranmer on Sunday November 08, 2020 @04:04PM (#25029027)

> they lacking TSX or SGX.

Note that the SGX instructions are system only, so the compiler isn't generating them usually. The hardware lock elision instructions in TSX are specifically chosen so that they act as NOPs on processors that don't support TSX.

[ Parent | on HN ]

Re:LLVM Clang 12 Merges Support For x86_64 Microarchitecture... by my123 on Sunday November 08, 2020 @04:35PM (#25029296)

Hardware lock elision was disabled via a microcode update. (see https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/lin...)

[ Parent | on HN ]

Re:LLVM Clang 12 Merges Support For x86_64 Microarchitecture... by throwaway2048 on Sunday November 08, 2020 @08:44PM (#25030659)

Not to mention TSX instructions have been broken in one way or another since their introduction, and now have been removed entirely in new intel silicon.

[ Parent | on HN ]

Re:LLVM Clang 12 Merges Support For x86_64 Microarchitecture... by my123 on Sunday November 08, 2020 @02:51PM (#25028385)

And assuming those are present for a given gen is even dumber sadly.

There are Comet Lake CPUs with no AVX at all: all Pentiums/Celerons.

Every 10th generation Intel CPU onwards, at least on the client side, doesn't support TSX.

[ Parent | on HN ]

Re:LLVM Clang 12 Merges Support For x86_64 Microarchitecture... by kevincox on Monday November 09, 2020 @08:33AM (#25034593)

I think it would have been even easier to understand if they used the launch year of the architecture. Of course you may need a finer number (include the month or just a count if there are multiple launches in a year?) but I think it is worth it to get a rough idea of how old something is without finding a lookup table.

[ Parent | on HN ]

Re:LLVM Clang 12 Merges Support For x86_64 Microarchitecture... by dragontamer on Monday November 09, 2020 @12:12PM (#25036961)

The details of chip releases is more complicated than just a numerical year.

FMA4 extensions on Bulldozer are no longer supported, so a 2012-era CPU supports FMA4, but 2018-era Zen processors do NOT support FMA4.

Xeon Phi supported a whole slew of AVX512 stuff that no other chip will ever support. Intel experimented with some instructions, and decided against them moving forward.

The point of a "vague" number, like "v3" is just to provide a general idea. Its purposefully vague, because the details are simply too messy to keep track of.

[ Parent | on HN ]

Re:LLVM Clang 12 Merges Support For x86_64 Microarchitecture... by kevincox on Monday November 09, 2020 @12:37PM (#25037258)

I never suggested that year should be precise. I just think it is useful to use year as a vague number instead of something completely arbitrary. I think the only real downside is if people assume too much from that number.

> FMA4 extensions on Bulldozer are no longer supported, so a 2012-era CPU supports FMA4, but 2018-era Zen processors do NOT support FMA4.

I don't see how this is relevant. Isn't this the same problem that v4 supports something that v9 doesn't?

[ Parent | on HN ]