Re:An ex-ARM engineer critiques RISC-V
by anp on Sunday November 01, 2020 @03:12PM
(#24962103)
Do any other ISAs have compressed encodings in wide use? It seems a bit like a chicken and egg problem - why build all the silicon to handle decoding it if your base ISA is dense enough?
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Re:An ex-ARM engineer critiques RISC-V
by pizlonator on Sunday November 01, 2020 @03:47PM
(#24962372)
Arguably x86 only has a compressed encoding in the sense that super common instructions often fit in fewer than 4 bytes and some of the most used ones are 1 byte. I don’t think the compression is deliberate or optimal though.
Re:An ex-ARM engineer critiques RISC-V
by saagarjha on Sunday November 01, 2020 @05:26PM
(#24963086)
Arguably most of the 1 byte instructions are garbage, though ;)
What, no love for AAA :-?
(IIRC they removed that one on x86-64)
Sounds pretty similar to thumb mode on ARM, no?
And ARM licensed the Hitachi SuperH patents when implementing Thumb. It's not exactly a new concept.
In addition to Thumb there are apparently at least MIPS16e ASE and PowerPC VLE.
ARM had Thumb, right? Is that a deadend at this point?
Thumb was removed from ARMv8 (AArch64). If you use 32-but legacy, it may exist on some chips; but it’s no longer the benefit it once was.
It's always been of the same value. You exchange performance for code density. They want aarch64 to be high-performance, so they removed thumb.
RISC-V compact instructions don't require special modes and run in fully-mixed mode with 32-bit instructions without all the penalties thumb has (they are literally just extended into their 32-bit counterparts internally).