Not obsolete yet, the technology is not mature enough, and the previous arguments against WSI are still valid.

People have been trying Wafer-Scale Integration [0] since the 1970s, there was quite some hype of building a "super chip" back at that time [1], but all efforts failed miserably. Cerebras' success is only the beginning, even if this approach is workable (which remains a question), there's still at least a decade to go from a HPC-specific chip to a general-purpose chip. Another possibility is that WSI will forever be a technology used in massively-parallel computers.

[0] https://en.wikipedia.org/wiki/Wafer-scale_integration

[1] Giant microcircuits for superfast computers, Popular Science, 1984. https://books.google.com/books?id=eAAAAAAAMBAJ&pg=PA66

I think it is important to separate the several technical failures in wafer scale from the commercial one: Sinclair's Anamartic worked exactly as planned but the prices for conventional hard disks began to drop and that caused investors to pull out.

http://www.computinghistory.org.uk/det/3043/Anamartic-Wafer-...

The problem is that the real project was a massively parallel computer just like the Cerebras (scaled to 1989 technological limits) and the disk replacement was just a way to develop the needed techniques and finance further developments. If the investors had had a little more patience then computing in the 1990s might have been a bit more interesting.

Another possibility is that the company will just fail, because it can not offer an advantage over commodity chips.

I already mentioned it,

> even if this approach is workable (which remains a question)

No need to repeat.

Not at all obsolete, defect rates rise exponentially as you increase die sizes, so wafer scale chips are stupid and wrong, but in financial sense only.

If you’re paying up for an entire batch and you only need one working example out of it, it probably matter less.

They disable bad parts of the die, like bad sectors on a disk.

At that point, is there really a benefit of having it all on one wafer, as opposed to just using chiplets?

Presumably there is, but wonder the same thing.

With wafer scale the amount of connections that can cross a border between two tiles is limited by the spacing rules for the top metal layers and by the number of layers you can dedicate to this (1 or 2, I would guess).

For TSMC N7 Design Rules[0] the pitch is 720nm for the top two metals (1388 wires per mm) and 76nm for the middle metal layers (13157 wires per mm).

In the case of chiplets on an interposer, if we suppose that the interposer can use a process similar to the top layers of the wafer then the number of wires between chiplets is the same. But you need pads and solder balls from the chipets to the interposer (and back on the other side). These pads can be in a grid pattern (like in a BGA package) so the area is the limit instead of perimeter. Let's be optimistic and suppose a pitch of 30µm for the copper pillar micro-bumps.

With a conservative 1000 wires per mm of perimeter the pads are not the limit with a chiplet larger than 3.6mm per side. With a more aggressive 10000 wires per mm the chiplets would have to be larger than 36mm per side, which is just beyond the reticle size limit of many chip fabs.

[0] https://en.wikichip.org/wiki/7_nm_lithography_process

This only works for some things, if you lose a clock or some part of the chip is just spewing garbage into whatever bus it’s using, you’re hosed.

They fuse it off