Cerebras Wafer Scale Engine Gen2 7nm 2.6T Transistors

Re:Cerebras Wafer Scale Engine Gen2 7nm 2.6T Transistors by evancox100 on Tuesday August 18, 2020 @10:18PM (#24206524)

Still wondering how they’ve handled interconnecting beyond each reticle limit/exposure. Are they staggering the exposures for each layer? And how do they handle packaging/IO/power delivery?

I guess these are the secret sauces and we are unlikely to get in depth information.

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Re:Cerebras Wafer Scale Engine Gen2 7nm 2.6T Transistors by gary_0 on Tuesday August 18, 2020 @11:16PM (#24206816)

In the PDF[0] that aveni linked above, they mention they "add wires across scribe line in partnership with TSMC, Extend 2D mesh across die". So the wafer isn't exactly one big chip.

[0] https://www.hotchips.org/hc31/HC31_1.13_Cerebras.SeanLie.v02...

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Re:Cerebras Wafer Scale Engine Gen2 7nm 2.6T Transistors by wmf on Wednesday August 19, 2020 @01:54AM (#24207557)

I think reticle stitching has been done previously in image sensors and silicon interposers so it may be an evolution of that.

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