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A comment on Intel Discloses Lakefield CPUs Specifications. Parent comment

Re:Intel Discloses Lakefield CPUs Specifications by stefan_ on Wednesday June 10, 2020 @03:31PM (#23481067)
There are processor architectures (MIPS) that can't do unaligned memory access where Linux will catch the fault, emulate the memory access in kernel and return to the program. On every unaligned access.

At least this only has to be done once, and frankly these AVX instructions are slow initially anyway.

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Re:Intel Discloses Lakefield CPUs Specifications by saagarjha on Wednesday June 10, 2020 @03:51PM (#23481274)
Yeah, and that was suuuper slow and everyone told you to not do it for exactly that reason…
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Re:Intel Discloses Lakefield CPUs Specifications by stefan_ on Wednesday June 10, 2020 @04:15PM (#23481557)
It's absurdly slow on hot paths, yet entirely unnoticeable to the vast majority of software out there.
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Re:Intel Discloses Lakefield CPUs Specifications by H8crilA on Wednesday June 10, 2020 @05:35PM (#23482424)
Most performance anti-patterns in almost any program are not important at all, as most of the code is not on the hot path.
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Re:Intel Discloses Lakefield CPUs Specifications by zokier on Wednesday June 10, 2020 @04:31PM (#23481724)
As it happens, MIPS is also practically dead as an general purpose architecture...
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Re:Intel Discloses Lakefield CPUs Specifications by sigotirandolas on Wednesday June 10, 2020 @08:46PM (#23483986)
It also happens on 32-bit ARM, which is maybe on its way out, but still way more common.
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Re:Intel Discloses Lakefield CPUs Specifications by loeg on Wednesday June 10, 2020 @03:50PM (#23481260)
And MIPS is slow as a dog, in part as a result of software handlers like this (software handles TLB and virtual memory walks, too, IIRC).
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Re:Intel Discloses Lakefield CPUs Specifications by gumby on Wednesday June 10, 2020 @06:00PM (#23482646)
> At least this only has to be done once, and frankly these AVX instructions are slow initially anyway.

FWIW I believe only some of them, and those are just some (or all?) AVX-512 instructions. I think AVX2 is implemented on the main die and doesn't have to be powered up first.

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Re:Intel Discloses Lakefield CPUs Specifications by celrod on Wednesday June 10, 2020 @09:19PM (#23484254)
https://travisdowns.github.io/blog/2020/01/17/avxfreq1.html

AVX (256 bit) instructions also suffer a penalty. Both the 256 and 512 bit instructions resulted in a slowdown for 9 microseconds featuring a quarter the instructions per clock, but the 512 bit instructions resulted in an additional penalty of 11 microseconds without executing instructions.

The first penalty was associated with voltage, and the second with frequency. Heavier 256 bit instructions would probably have resulted in the frequency transaction as well.

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