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A comment on Intel Discloses Lakefield CPUs Specifications. Parent comment

Re:Intel Discloses Lakefield CPUs Specifications by gumby on Wednesday June 10, 2020 @06:00PM (#23482646)
> At least this only has to be done once, and frankly these AVX instructions are slow initially anyway.

FWIW I believe only some of them, and those are just some (or all?) AVX-512 instructions. I think AVX2 is implemented on the main die and doesn't have to be powered up first.

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Re:Intel Discloses Lakefield CPUs Specifications by celrod on Wednesday June 10, 2020 @09:19PM (#23484254)
https://travisdowns.github.io/blog/2020/01/17/avxfreq1.html

AVX (256 bit) instructions also suffer a penalty. Both the 256 and 512 bit instructions resulted in a slowdown for 9 microseconds featuring a quarter the instructions per clock, but the 512 bit instructions resulted in an additional penalty of 11 microseconds without executing instructions.

The first penalty was associated with voltage, and the second with frequency. Heavier 256 bit instructions would probably have resulted in the frequency transaction as well.

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