Actually it does.

BSF (Bit Scan Forward) is the most famous which returns an undefined result if your operand is 0.

Many instructions leave the state of bits in the FLAGs register undefined. E.g. AAA will leave SF,ZF, and PF undefined.

Then of course there is the “reserved bits” but those are easier to avoid.

Here's a 6502 instruction that has undefined behavior, because the microsequence connects circuits together in an invalid way causing analog effects that can change even run to run of the same processor.

http://visual6502.org/wiki/index.php?title=6502_Opcode_8B_%2...

It looks like that’s not undefined behaviour, but using a non-existent and undefined opcode, which happens to “do something” because the cpu attempts to execute the bits anyway (it doesn’t mask the unused opcodes into no ops or errors). Later variants of the 6502, like the WDC 65C816, did away with this (I believe, either using the opcodes for something defined, or making them no ops, although I’m unsure)

"Of all the unsupported opcodes" - I'm not sure it's a good example.

It does, what it lacks is an optimizer that will rewrite your code to win micro-benchmarks, just because it happened to be UB.

It sure does.

Some is inherent to the ISA itself.

And some undefined behavior is errata that differs from CPU to CPU. Check out the errata documentation for any processor released in the last few decades. For example, x86. You can trigger things that happen on one x86 CPU that won't happen on another.

Not entirely true. Look up 'Silicon Errata' and you will find some examples. Its actually interesting stuff