I built one off the same infrastructure called hideCPU. If you can create AND/XOR/NAND/etc gates _and_ feed-back output into your input, you can create a CPU.
https://github.com/mmastrac/oblivious-cpu
My goal was more to build some open prior art in the space rather than actually build a viable FHE CPU, but there's no reason why you couldn't implement one of these on top of the FHE system.
To answer some statements about FHE computing that come up over and over:
- Yes, you can loop + perform control flow in a FHE-based computer
- Yes, you can recurse in a FHE-based computer as long as you have enough emulated RAM/stack
- Yes, you can store state in a FHE computer
- No, you cannot determine if a FHE computer has reached a certain state (or halted) from the outside without decrypting the system (or at least a state bit)
- Yes, you can emulate RAM in a FHE computer
- Yes, you can emulate a HDD (well, rotating storage) in a certain FHE computer constructions
How does your implementation compare?
I am sure I had a stat for the longest path from input to output, but I'm a few years swapped out on this project.
Note that adding pipelining to a CPU drastically reduces the longest path. ShapeCPU is not pipelined at all which probably means there's a bunch of low-hanging fruit.
Because we use chisel to write CPU and we also made LLVM backend for our original CPU, your idea is not so difficult although it may be very slow. Our original CPU is about 4K gates. The most difficult point is building memory because it is most slow part. We used TFHE's LHE mode for it and this is one of the novel points of our work.
(We didn't know about Shape CPU but it seems to be similar to FURISC, which is published and using libScarab.https://eprint.iacr.org/2015/699)
Encrypted termination conditions were definitely in that implementation. The memory mux too.
By the way, I feel sad for there is no publication of ShapeCPU. I guess that this is one of the causes of FURISC paper is lacking reference for ShapeCPU.
Lots of prior art in that implementation!
Any control flow program, on a set of inputs for which it terminates[0], can be, but it's not true that any control flow program, with unspecified inputs, can be, even with variables for the inputs, since the shape of the multiplication as well as the value of elements in the matrices may depend on the inputs (also, whether it's even a terminating program can obviously depend on the inputs.)
[0] and any program which always terminates can also be, though the general form may be more complex than is necessary for some inputs.
Non-terminating programs are modelled as infinitely-sized matrixes, which are obviously not computable; but neither are non-terminating programs computable in the real sense.
Would it perhaps be possible to create a weaker form of homomorphic encryption that could branch? It would not be strong enough for the most serious security use cases (authentication, financial, etc.) but would perhaps be usable for cases where you just want to protect data confidentiality e.g. processing PII. The processor could probably infer the structure of the running program but not necessarily its data if appropriate constant-time comparisons and other constructions were used.
Ergo, you can model anything CPUs do as a matrix.
If you wouldn't mind reviewing https://news.ycombinator.com/newsguidelines.html and sticking to the rules when posting here, we'd be grateful.
I don't think so, but not sure.
CONSTANT NOT COPY NAND OR AND XOR XNOR NOR ANDNY ANDYN ORNY ORYN MUX
... so pure, combinational logic operators. You can build up some serious functions with these, yes.
Has it been done?