nindanaoto

I'm also doubting that but before I knew Shape CPU, I believed because FURISC seems to be based on HEROIC, which is claimed to be the first processor emulation over homomorphic encryption. https://past.date-conference.com/proceedings-archive/PAPERS/... I think FURISC is more like HEROIC than ShapeCPU.

By the way, I feel sad for there is no publication of ShapeCPU. I guess that this is one of the causes of FURISC paper is lacking reference for ShapeCPU.

TFHE is known to be switchable between other RLWE based Homomorphic Encryption. https://eprint.iacr.org/2018/758 Glyph applied it to accelerate deep learning, but they use integer level, not float. https://arxiv.org/abs/1911.07101

AFAIK, Homomorphic Encryption which supports floating point arithmetic is not known. Fixed point one is known, CKKS. https://github.com/snucrypto/HEAAN

Cingulata currently supports TFHE. https://github.com/CEA-LIST/Cingulata/wiki#headlight We also used Yosys to convert Chisel into JSON netlist. It is easy to use. I hope this may help. This is archived but simple. https://github.com/virtualsecureplatform/V2TT

This may be enough, right? https://tfhe.github.io/tfhe/gate-bootstrapping-api.html

Yes, it can be stateful. We built processor

Our original CPU, CAHP-emerald is 5 stage pipeline, super-scalar processor. Pipelining improved performance well. https://github.com/virtualsecureplatform/cahp-emerald

We made our original CPU&ISA emulator over TFHE. https://github.com/virtualsecureplatform/kvsp

Because we use chisel to write CPU and we also made LLVM backend for our original CPU, your idea is not so difficult although it may be very slow. Our original CPU is about 4K gates. The most difficult point is building memory because it is most slow part. We used TFHE's LHE mode for it and this is one of the novel points of our work.

(We didn't know about Shape CPU but it seems to be similar to FURISC, which is published and using libScarab.https://eprint.iacr.org/2015/699)