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A comment on Reviewing Bad Schematics as EE Interview Tactic.

Re:Reviewing Bad Schematics as EE Interview Tactic by analog31 on Monday December 23, 2019 @06:10PM (#21868330)
>>> Then, you give them a fake schematic of the circuit board, and ask them to troubleshoot the problem.

Is the board built to the schematic?

That's my first question when a board loses its magic smoke.

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Re:Reviewing Bad Schematics as EE Interview Tactic by imba404 on Monday December 23, 2019 @10:28PM (#21869612)
That in itself is a Design for Manufacturing question, involving stack-up, Gerber correctness, and drill tolerances.
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