Secondly, because the people who understand FPGAs are hardware engineers the tool vendors hire hardware engineers (and software engineers who are willing to tolerate hardware engineers) to write their software, the result is tools written using the development practices of the dark ages.
End of rant.
You have software languages as well where "every line of code runs concurrently". Any dataflow framework for instance. That's not even to name functional languages where evaluation of statements can be done completely in parallel based on data dependencies.
Software is a lot more then the old c style run a program line by line until it hits the end of main().
Sounds like Clash! It's pseudo-Haskell that compiles to Verilog or VHDL.
If you want to go really bonkers, there’s spatial-lang which allows easy interop with the Java memory model and heap
There are a few businesses that use Haskell to target FPGAs.
And yes, it's all about parallelization. As the docs also say, this only makes sense if your algorithm is embarrassingly parallel. If you check out the examples are like this too (within the limitations of a small FPGA).
BTW "programming" an FPGA in my understanding is the process of flashing the bitstream onto the board.
mmult mA mB = result
where
mBT = transpose mB
dot a b = sum $ zipWith (*) a b
result = map (\ar -> dot ar <$> mBT) mA
it's really gonna take xilinx or altera to innovate in this space, but that is unlikely any time soon.
I think people already use Clash/Haskell to write HDL.
So, other than a headline I’m not seeing any advantage over Verilog or VHDL to consider this at all. I think there is a much larger issue in people not understanding FPGAs than the code used to configure them.
You program what needs to go into the FPGA by writing RTL, then you synthesizes the RTL, then you configure them at powerup time.
This subject of this topic is about using .NET as an alternative to traditional RTL languages. That's programming. If you're going to call that configuration, you're overloading a term "configuration" in a way that nobody in the FPGA industry ever does.
Programming is setting the knobs on the machine, working with an existing structure to get a job done.
Configuring an FPGA is laying out the machine. You are designing the hardware gates and building the structure.
You could argue it’s pedantic, sure. But I think that’s 90% of the reason people struggle with FPGA is they look at it like programming and not hardware design. I was explained this difference by people in the FPGA reverse engineering industry.
So, no to the topic, I still see zero reason to use a .NET programming language to shoehorn how you want mostly non-procedural hardware logic to function. Other than to say you did it and write an article about it.
When your program in Verilog, the knobs are the bits of a bunch of LUTs.
Insisting to call it configuration is not only pedantic. It is also not used this way by anybody else. And it’s confusing because it overloads a term that is used universally by all FPGA tools.
It’s hard to see how that makes it any different than just wrong.
Imagine the following conversation in isolation:
“Hey John, what are doing today?” - “I’m configuring my FPGA!”
Ask anyone in the field what is being described above. I guarantee you that nobody would answer that John is writing RTL.
also, i don't really understand how moving something that is compute bound down to an FPGA is what you do. FPGAs are slow compared to CPUs. where they help is if you have something that can be parallelized and/or you want it to happen in a real-time manner.
it would be a big win if there was a more modern HDL language. VHDL actually has a lot of nice features. however, i think a cross with it and an ML language (like F# or OCaml) would be a wonderful fit for programming FPGAs, that is designing (or at least dictating) hardware with software.