RISC-V formal spec public review

Re:RISC-V formal spec public review by Dylan16807 on Friday June 21, 2019 @01:49AM (#20240174)

There are instructions to get the top half of a multiply, and a suggested ordering so that the chip can deliver both halves with only one calculation.

There's no carry flag but I'd say it's still easy to work around that.

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Re:RISC-V formal spec public review by waterhouse on Friday June 21, 2019 @04:10AM (#20240788)

Specifically, I think the "sltu" (set if less than, unsigned) instruction is useful for carries. When you add two unsigned integers, the result is smaller than the inputs if and only if an overflow occurred.

  ; a1:a0 * a2 --> a5:a4:a3
  ; using t0 as temp reg
  mulhu a5, a1, a2
  mulu  a4, a1, a2
  mulhu t0, a0, a2
  mulu  a3, a0, a2
  add   a4, a4, t0
  ; carry a 1 or a 0, overwriting t0
  sltu  t0, a4, t0
  add   a5, a5, t0

(edit: switched a1 and a0 for consistency)

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