Chiplets and power are the next dimension of competition. Yield, chiplets vastly improve yield. The limit as chiplet size drops, yield basically goes to 1. Erasure Coding for Silicon.

And then power, part of that is process and part is design. I am not skilled enough to call that, but as leakage current drops, then does power draw, static power draw, allowing for frequencies to scale over larger ranges. Hell, maybe went with some novel clockless design.

Either way, this is momentous.

I didn't see any news about leakage being resolved, do you have an article ?

clockless and low power.. exciting

It was supposition based on the power differences, I only do armchair solid state physics.

better than bedroom solid state physics I guess