SymbiFlow: A FOSS Verilog-to-Bitstream FPGA synthesis flow for Various FPGAs

Re:SymbiFlow: A FOSS Verilog-to-Bitstream FPGA synthesis flo... by ur-whale on Tuesday October 09, 2018 @07:58AM (#18175150)

Not too happy with the "will be" part, because these types of endeavors are really hard, and it's unclear what likelihood of success the project has.

But apart from that ... I really wish these guys will be successful.

The FPGA world sorely needs to open up.

My favorite analogy is that the FPGA world (and the ASIC design world in general) needs a project equivalent to LLVM: something that sorts out once and for all all the gnarly and nasty low-level stuff, offering a consistent high level view of hardware (a hard feat of course, given how different H/W might be from one vendor or chip gen to the next, but LLVM did pull it off) - even if it's not as optimal as coding down to the metal would be - and lets the rest of the world build amazing, high-level tech. on top of it.

As a matter of fact, I really wish they had a link on their page to tell people how the project can be helped.

[ Parent | on HN ]

Re:SymbiFlow: A FOSS Verilog-to-Bitstream FPGA synthesis flo... by pjc50 on Tuesday October 09, 2018 @08:45AM (#18175436)

That commoditizes the FPGA market. Which is great for consumers but the exact thing the manufacturers hate, because suddenly they have to compete on price because it's easier to switch tooling.

If Intel thought they could get away with requiring a licensed compiler for their processors, they would. GPUs are in the no-mans-land: somewhat portable shader languages, but the compiler targets are proprietary and rapidly shifting.

[ Parent | on HN ]

Re:SymbiFlow: A FOSS Verilog-to-Bitstream FPGA synthesis flo... by ur-whale on Tuesday October 09, 2018 @10:18AM (#18176160)

It's pretty obvious the manufacturers will try and get away with vendor lock-in for as long as they can.

NVidia has been playing that game with Cuda from day one, leaving OpenCL as a barely supported, barely usable, and complete no-no for anyone who wants to do production work with their hardware so they can avoid this very criticism.

The manufacturers are the villain in that story, and they know it.

This makes the kind of project described in the OP all the more important, and the folks who work on it should get help form anyone who uses FPGA's commercially.

[ Parent | on HN ]

Re:SymbiFlow: A FOSS Verilog-to-Bitstream FPGA synthesis flo... by analognoise on Tuesday October 09, 2018 @04:55PM (#18179745)

I work with FPGAs commercially. Using non- supported tools isn't an option.

If you're building anything 'real', you're not going to try to save a few thousand dollars and risk the program, you just cost it in.

Yeah, I know, Synplify costs way more than that, it isn't exactly standard anymore (Xilinx' tools got good enough).

It's really not that expensive, considering the FPGA is usually critical system architecture.

I don't see Nvidia as the 'villain' in that story either - they designed the graphics chips, they designed Cuda. Nobody is forcing anyone to use either. They don't support the language you like? Use somebody else's chips. They can't support every language - I'm not upset they don't directly support Object Pascal.

[ Parent | on HN ]

Re:SymbiFlow: A FOSS Verilog-to-Bitstream FPGA synthesis flo... by fpgas4ever on Tuesday October 09, 2018 @10:53PM (#18181602)

The SymbiFlow project seems to have an "ideas" repository at https://github.com/SymbiFlow/ideas/issues

@mithro on twitter (https://twitter.com/mithro) sometimes posts requests for help like https://twitter.com/mithro/status/1018270467545706496 || https://twitter.com/mithro/status/1012113316385132545 || https://twitter.com/mithro/status/1010702164790874113

Maybe someone needs to help them do a better website!

[ Parent | on HN ]

Re:SymbiFlow: A FOSS Verilog-to-Bitstream FPGA synthesis flo... by TD-Linux on Tuesday October 09, 2018 @12:22PM (#18177273)

The site is actually a bit out of date, the ECP5 bit (Project Trellis) and nextpnr are already working:

https://github.com/YosysHQ/nextpnr

[ Parent | on HN ]

Re:SymbiFlow: A FOSS Verilog-to-Bitstream FPGA synthesis flo... by analognoise on Tuesday October 09, 2018 @04:59PM (#18179766)

I thought not all the blocks of the FPGA were available yet - block rams were just recently added, but I think some of their clocking tiles are not fully operational.

Could be outdated info though, if someone knows can you provide a link?

[ Parent | on HN ]

Re:SymbiFlow: A FOSS Verilog-to-Bitstream FPGA synthesis flo... by fpgas4ever on Tuesday October 09, 2018 @10:44PM (#18181568)

On of the developers of SymbiFlow gave a high level update at OrConf 2018 (https://orconf.org) recently. I believe it was recorded but haven't seen any info of when they will be published. You can find the slides at https://j.mp/orconf-symbiflow but it is a little cryptic without narration.

The guy working on the ECP5 stuff also gave an in-depth dive into how that part works but I can't find a link to his slides.

[ Parent | on HN ]