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A comment on SymbiFlow: A FOSS Verilog-to-Bitstream FPGA synthesis flow for Various FPGAs. Parent comment

Re:SymbiFlow: A FOSS Verilog-to-Bitstream FPGA synthesis flo... by analognoise on Tuesday October 09, 2018 @04:59PM (#18179766)
I thought not all the blocks of the FPGA were available yet - block rams were just recently added, but I think some of their clocking tiles are not fully operational.

Could be outdated info though, if someone knows can you provide a link?

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Re:SymbiFlow: A FOSS Verilog-to-Bitstream FPGA synthesis flo... by fpgas4ever on Tuesday October 09, 2018 @10:44PM (#18181568)
On of the developers of SymbiFlow gave a high level update at OrConf 2018 (https://orconf.org) recently. I believe it was recorded but haven't seen any info of when they will be published. You can find the slides at https://j.mp/orconf-symbiflow but it is a little cryptic without narration.

The guy working on the ECP5 stuff also gave an in-depth dive into how that part works but I can't find a link to his slides.

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