Even 600nm is commercially viable for specialty applications, 300nm for low-end general purpose, and their aim is 180nm. So there is nothing about the process itself that disqualifies it.

Heck, with immersion lito you can even use DLP chip(s) with 405nm and then-trivial multi-patterning to the 180nm... likely even close to 130nm, but that's a stretch that might be too hard on the compensation. This sort of node, with no minimum order quantity and pricing within 2~5x of mask-based fab (slightly slower steppers at these scales, but 600nm might be still reachable in 2 minutes on a 12" for the exposure if you use some resonance or so to get sawtooth-motion of the head to e.g. compensate for a spinning wafer (think like a record/CD player unless viewed in slow motion). Resonance is surprisingly easy to keep steady-state with just a piezo and maybe another one if needed that provides all high frequency content that's not handled by the fundamental and 2 or 3 low harmonics of the scan frequency.

There are applications thanks to modern automation as far as hard-wired logic instead of a via mask ROM, and this should be able to eat much of the low-end FPGA business due to even just much higher design flexibility.