We (or more likely, Clifford Wolf) writes the code to do it. Maybe not today, but proprietary software wasn't replaced by open source software in a day.
I'm not saying that yosys is a replacement for Vivado, it's obviously not, but here we have a nice Artix-based board and with not too much effort we could also offer a completely free, easy to use toolchain for it, perhaps not one which does everything, but definitely enough to download designs, compile a bitstream and program it onto the board.
Instead we have this huge barrier to entry - download 40GB [sic] of proprietary crap and register for a time-limited account which is tied to the particular chip you're using.
Actually, you kinda did:
>>> Please let's kill off Vivado once and for all. [...] There are open source tools for programming FPGAs, and they are really great too: https://rwmj.wordpress.com/2018/03/17/playing-with-picorv32-...
Right, and my truck runs on dreams and starlight.
It’s not the the open source doesn’t work, it usually does, and the small size of it is really nice, it’s that it doesn’t come close in terms of debugging functionality when things go wrong.
My current workflow is to always develop using Quartus first, and only when things work perfectly I move it over to ICE40.
But even then I sometimes have an identical mid sized RTL design that works perfectly on my small Altera and Xilinx boards, and it just doesn’t work on my ICE40 board.
How do I debug this?
There is no easy signaltap or chipscope route. I just have to guess and hope for the best.
Unfortunately, what also doesn’t help is that all those cheaper Lattice FPGAs are woefully outdated. And their newer ones aren’t supported by open source tools yet.
I hope things improve fast, but for now, I’d advise hobbyists who are getting their toes in the water to use closed sourced tools.