It’s not the the open source doesn’t work, it usually does, and the small size of it is really nice, it’s that it doesn’t come close in terms of debugging functionality when things go wrong.

My current workflow is to always develop using Quartus first, and only when things work perfectly I move it over to ICE40.

But even then I sometimes have an identical mid sized RTL design that works perfectly on my small Altera and Xilinx boards, and it just doesn’t work on my ICE40 board.

How do I debug this?

There is no easy signaltap or chipscope route. I just have to guess and hope for the best.

Unfortunately, what also doesn’t help is that all those cheaper Lattice FPGAs are woefully outdated. And their newer ones aren’t supported by open source tools yet.

I hope things improve fast, but for now, I’d advise hobbyists who are getting their toes in the water to use closed sourced tools.

We (or more likely, Clifford Wolf) writes the code to do it. Maybe not today, but proprietary software wasn't replaced by open source software in a day.

I'm not saying that yosys is a replacement for Vivado, it's obviously not, but here we have a nice Artix-based board and with not too much effort we could also offer a completely free, easy to use toolchain for it, perhaps not one which does everything, but definitely enough to download designs, compile a bitstream and program it onto the board.

Instead we have this huge barrier to entry - download 40GB [sic] of proprietary crap and register for a time-limited account which is tied to the particular chip you're using.

Actually, you kinda did:

>>> Please let's kill off Vivado once and for all. [...] There are open source tools for programming FPGAs, and they are really great too: https://rwmj.wordpress.com/2018/03/17/playing-with-picorv32-...

Right, and my truck runs on dreams and starlight.

But, Vivado does a lot of very valuable things in practice that will take a lot of time to really replace properly, if you're doing serious FPGA work for Xilinx systems. Or even if you're doing semi-serious work. A working flow is one thing, killing it off is a much harder challenge.

Even for Lattice FPGAs, IceStorm does not match e.g. Lattice iCEcube2 in terms of features or functionality (timing analysis reports, power estimation, floorplan and pinout UXs, very standard clock synthesis and constraint options, etc etc.) But it's way better at the things it actually does, admittedly. Despite that, I still find myself reaching for iCEcube2, even if my actual flow is IceStorm. These are all fixable and you can live without them, but that's for a simple EDA tool on the simplest/cheapest consumer FPGA you can buy, with a limited technology library and hard IP.

The ongoing move to use tools like VPR however will polish a lot of that off (power/timing/clock constraint synthesis). XRay will benefit from that. The rest is going to be a lot of IP cores, simulation models, middleware, and software tooling, and that's what's needed to really kill off something like Vivado.

Debugging tools are probably the most important middleware in particular, and they are sorely lacking.

Personally at least, I will say Yosys is IMO the nicest synthesis tool there is. So, if you are OK with Verilog, the FOSS community does have some best-in-class tools already. :)

This must be the weekly "Give beginners terrible advice" thread.

I might be missing something, but is that Virtex 7 or Artix 7 ? From the project page, it looks like Artix, and that's great since many hobbyist level entry boards use Artix 7, like Arty, Basys and Nexys (at the upper end)

It's fine now, or at least as 'fine' as FPGA tools ever get. Much better than ISE ever was. In any case, there is currently no alternative if you're looking at using a Xilinx part that is supported only by Vivado and not ISE.