I.MX7 M4 Atomic Cache Bug

Re:I.MX7 M4 Atomic Cache Bug by ChuckMcM on Sunday February 18, 2018 @04:17PM (#16408728)

In that thread -- After reproducing the issue and performing some tests, it was found that the issue is because “LDREX” and “STREX” instructions overlooked LMEM cache. That means those instructions always access external memory directly, which leads to data inconsistency.

There’s no SW configuration to make the cacheable data consistent with those atomic instructions, and design team will fix it in later CM4 integration.

Its a bug. But they see a workaround so they aren't in a hurry to fix it apparently.

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Re:I.MX7 M4 Atomic Cache Bug by Gibbon1 on Sunday February 18, 2018 @05:29PM (#16409198)

That reminds me of an article about a similar problem with the xbox. Cache consistency is extremely brittle combine that with speculative execution and that means just having instructions that break cache consistency in memory is dangerous.

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Re:I.MX7 M4 Atomic Cache Bug by Dylan16807 on Sunday February 18, 2018 @06:07PM (#16409425)

Here you go:

https://randomascii.wordpress.com/2018/01/07/finding-a-cpu-d...

https://news.ycombinator.com/item?id=16094925

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