Linux page table isolation is not needed on AMD processors

Re:Linux page table isolation is not needed on AMD processors by rurban on Tuesday January 02, 2018 @12:45PM (#16053598)

Nope, read the paper, read the patches. Only Intel is affected. Arm has two such registers, TTB0 and TTB1. http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc....

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Re:Linux page table isolation is not needed on AMD processors by amluto on Tuesday January 02, 2018 @01:14PM (#16053862)

I think you're still misunderstanding. The CPU picks TTBR0 or TTBR1 based on the top significant bit of the VA, irrespective of whether the access was initiated by user or kernel code. This is in contrast to s390, which has separate page tables for user mode and kernel mode. I personally much prefer s390's model.

And yes, I've read quite a few papers, and I wrote a good fraction of the patches.

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Re:Linux page table isolation is not needed on AMD processors by rurban on Tuesday January 02, 2018 @01:35PM (#16054081)

Oh, thanks. My fault then. I haven't read the arm patches, only the summary.

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Re:Linux page table isolation is not needed on AMD processors by kev009 on Wednesday January 03, 2018 @02:55AM (#16059312)

I vaguely remember some threads from last decade where Linus trashed PowerPC and s390 TLBs. I wish I could find them and reread with this in mind.

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Re:Linux page table isolation is not needed on AMD processors by stefanfisk on Friday January 05, 2018 @03:50PM (#16081512)

are you thinking of this? http://yarchive.net/comp/powerpc_page_tables.html

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