Also everyone is welcome to review our code and to contribute to the codebase. It is an open source project. IIT-M incubated it but we want it to be community driven. FPGA based dev packages should be announced by jan , based on standard low cost FPGA boards. Dev parts based on ASIC parts will probably be announced 2nd quarter of next year assuming Feb/March tapeout.We would be glad to help other universities do their own tapeouts. One of the goals of Shakti is also to demystify the backend process.

Congratulation on the project. Where can one find the source? Is this the one? https://bitbucket.org/casl/shakti_public

Yes, we will update the C Class next month since our private line has a lot of foundry specific code that needs to be removed. The I class needs more work but the design is in place. It will also move to quad issue and would be a Cortex A72/75 class core. More importantly the basic slow IPs, UART, I2C, quad/Octal SPI, SDRAM controller, JTAG, DMA, PLIC will be FPGA and silicon proven and production quality. Will be very useful to other developers (non RISC-V also) as would the AXI bus.

You said "open source Rust based MK OS..." Does that mean an OS written in Rust? I had not heard of that. As I recall the Rust support for RISC-V is quite limited for now until the LLVM patches go upstream (which will be soon).

I agree with your statement "I have no idea how successful we will be and I frankly do not care." There will be a lot of benefits as a result of this work regardless of the immediate outcome. Keep building the future!

There are a lot of comments here on HN that seem completely uninformed of what's actually happening with RISC-V. They are about to be surprised.

Rust support is getting better. Our Rust OS is lower priority but it is needed for our tagged ISA support since we need language extensions to add security semantics to pointers. Also Rust is a much safer language. We need all this since safety critical systems is a key Shakti target.

Is this similar to the stuff lowrisc is doing?

Yes, we are also collaborating with them. The HW is the simpler problem to solve. SW life-cycle for creating tags, embedding them in the code and ensuring that teh binary has not been tampered is the challenge and to ensure portable tag semantics. We have a dedicated security group working on it. Unlike US universities we have carte blanche for hiring faculty and scholarships for MS/PhD. Funding is not the issue, getting good faculty and students is ! Some of you should head over here for an MS or PhD.

Thanks for the clarifications - always good to hear from the source.

I think there are many people waiting for some real RISC-V ISA silicon. The existing chips are really under powered samples at this point. So, this article made me glad to see this announcement.

That is what the team is spending is spending its time on, PPA optimization so that we have a good idea how far we can go. Iterating with as many process corners as possible to get the right compromise.. But we have to be careful, it is a new low power process node. The backend team is a very accomplished team from a leading VLSI design services entity who are helping us out. That team is also doing a 7nm tapeout simultaneously for a commercial customer, so they know how to route a chip ! Take apart a flagship mobile phone and you will see their handiwork. It is not a bunch of students trying their hand at PnR. Our team sticks to the architecture, design, coding and verification since these are our core strengths. We also get our work audited by external entities. Bottom line, we are as professional and process oriented as any commercial outfit.

I got a lot of emails regarding Shakti's positioning. As can be seen from our webpage, specific cores have been positioned to offer alternative to commercial cores including ARM's cores. Whether ARM gets affected by this or not is not for me to say. But to conclude that SHAKTI and the RISC-V eco-system in general could affect ARM significantly is not an unreasonable conclusion.So the reporter is well within the realm of reason to arrive at the conclusion he did. I am just making a distinction between causal reactions and intent !

>3. The CPU eco-system including ARM's is a bit sclerotic. It is not the lic cost that is the problem, it is the inherent lack of flexibility in the model.

When not even Google can get a CPU without built in IME/PSP "secure" processors running insecure code, that seems like an understatement.

It seems like almost everyone is ignoring the epic fallout of a truly malicious entity discovering and silently exploiting a remotely exploitable security hole in for example Intel ME. They could more or less shut down whole countries by a key press.

And that would be just the start. When you can't be sure if there is malicious software remaining deep inside your processors, you pretty much have to shred them. And the motherboard, and the disk drives (http://spritesmods.com/?art=hddhack), etc. You simply would have to replace your whole IT-infrastructure. Then you need to try to figure out what sensitive data was lost... It would be a nightmare for sure. If I were Google or Amazon I would be absolutely paranoid.

How much will it cost for USA to implement a replacement for Social Security Numbers after the Equifax leak?

As our dependence on IT increases it becomes a more attractive target, so a well protected IT-infrastructure will be an absolute necessity in the near future. To be able to build a secure infrastructure, we need a hardware foundation that we can trust. We simply don't have that today!

Shakti sounds like it can be the foundation we need, I very much hope so.

if you haven't seen it: https://www.youtube.com/watch?v=PLJJY5UFtqY

He's a security expert working for Google. Here he is explaining just how bad the situation is.

here he talks about lack of trustable CPU:s https://youtu.be/JCa3PBt4r-k?t=7m22s

Thank you for all the efforts. I am interested in MCU synthesis on FPGAs and this is a really interesting project.

I just have one request though. If you are interested in Makers taking interest in your project please make sure your documentation is top quality. Also try to provide cheap dev boards so that the community can provide Linux or some RTOS port. I being in India it would help immensely if you have your dev resources at lower costs(FPGAs which I really doubt but dev boards with your processor, yes) so that people like me can help you with some OS ports. You can also follow the route of Adapteva Inc which can provide you with a template of good quality product (i.e. Good documentation, source code etc).

I am very much interested in the maker community and would certainly do whatever it takes to engage that segment. Doc is th Achilles heel of efforts like ours and we intend to address that. Our code for example is extremely well commented and structured.We have 20 character variable names !We work with Xilinx, Altera and Microsemi and will target low cost dev boards but more importantly also tapeout ASICs for arduino boards.But first need to focus on our tapeouts.

This looks very interesting. Its high time an Indian institution has some framework for designing semiconductor chips from scratch and perhaps even mass manufacture them for selling them to the rest of the world.

My question is about Bluespec SV and the random logic synthesis of the written code. Is it good enough for good power consumption figures or is that not really a concern at this point? Do you know how its reception has been in industries in the last 4-5 years? Is it still the 'technology of the future'?

Another question I have is, this project being open source, are you seeing contributions from other educational institutions or industries? What would be needed get more institutions involved?

That sounds like an ambitious project, I hope it becomes a success!

I think the world can use some competition in the server space between different ISAs, the current Intel(-and-sometimes-AMD) monoculture is problematic for a number of reasons.

> 3. The CPU eco-system including ARM's is a bit sclerotic.

Silly question, but what do you mean by "sclerotic" here? I had to look up the word and only found medical definitions.

I looked it up too. It also means 'rigid and unresponsive'