Re:The Mill CPU Architecture: Switches [video]
by CyberDildonics on Wednesday July 19, 2017 @10:49AM
(#14804655)
What makes you think you can extract that much instruction level parallelism in the first place?
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Re:The Mill CPU Architecture: Switches [video]
by willvarfar on Wednesday July 19, 2017 @11:29AM
(#14804986)
One major one is speculation. Each Mill operand, or element in a vector operand, has a 'Not a Result' (NaR) flag.