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Re:The Mill CPU Architecture: Switches [video] by igodard on Wednesday July 19, 2017 @10:24AM (#14804453)
Mill has no register file, and is essentially a bypass network internally. That bypass network has a source X sink complexity (not N^2 because the number of sources need not match the number of sinks). You are right that the cross product is a limit on Mill scaling. Our internal work gives us some confidence that we can handle 30-wide issue with tolerable clock impact; beyond that is unclear, and indeed we may hit other constraints that preclude going further; memory bandwidth is a likely issue.
Re:The Mill CPU Architecture: Switches [video] by CyberDildonics on Wednesday July 19, 2017 @10:49AM (#14804655)
What makes you think you can extract that much instruction level parallelism in the first place?
Re:The Mill CPU Architecture: Switches [video] by willvarfar on Wednesday July 19, 2017 @11:29AM (#14804986)
One major one is speculation. Each Mill operand, or element in a vector operand, has a 'Not a Result' (NaR) flag.
Re:The Mill CPU Architecture: Switches [video] by thesz on Wednesday July 19, 2017 @11:37AM (#14805040)
You still have quadratic complexity of the network, the "need not match" argument can be reduced to a constant multiplier.