Decades of optimization on a crap architecture. The Mill has been able to learn from the mistakes made in every architecture to date. The kind of comparison you make doesn't mean anything as a result.

Intel has also learned from each generation.

CISC is very efficient. They do the most ops per transistor.

But Intel is constrained by backwards compatibility.

"CISC is very efficient" is a meaningless statement. The specific instruction set and its implementation is or is not efficient.

Disclaimer: Opinions are solely my own and do not reflect my employer's