It sort of depends on coding style - if you're hand instantiating gates and wiring them in verilog then yes it is a lot like assembly ... on the other hand if you're coding in a high level way and having your design compiled to gates then no, it's not at all like assembly

It also may depend on where you learned your craft - my decade as a logic designer seemed to show people who started life as an EE and went straight into logic design coded at a lower level than people who started as programmers (who tended to be more productive as a result) ....

Does your comment imply that people who started as programmers tended to be more productive at FPGA design?

Well (from a VERY VERY small sample) I think yes (I was referring more generally to people doing logic design in Verilog, not just FPGAs) - in my experience they tended to write at a higher level and knock out gates faster .... that left them with more time to optimise their designs

But this is old data - the world changes

In my experience although limited most software developers write terrible HDL code. They think too serially, step wise, and aren't very good at parallelizing their code on the level necessary for good hardware design.

The exception to this are those with good hardware sympathy. They can after carry over that detail oriented thought process.

Maybe, but I'm not talking about beginners here, I'm talking about people who already have years of experience