Program FPGAs with Go

Re:Program FPGAs with Go by Taniwha on Tuesday June 13, 2017 @08:42PM (#14549948)

Well (from a VERY VERY small sample) I think yes (I was referring more generally to people doing logic design in Verilog, not just FPGAs) - in my experience they tended to write at a higher level and knock out gates faster .... that left them with more time to optimise their designs

But this is old data - the world changes

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Re:Program FPGAs with Go by jnordwick on Tuesday June 13, 2017 @10:00PM (#14550212)

In my experience although limited most software developers write terrible HDL code. They think too serially, step wise, and aren't very good at parallelizing their code on the level necessary for good hardware design.

The exception to this are those with good hardware sympathy. They can after carry over that detail oriented thought process.

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Re:Program FPGAs with Go by Taniwha on Wednesday June 14, 2017 @12:26AM (#14550639)

Maybe, but I'm not talking about beginners here, I'm talking about people who already have years of experience

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