VHDL or Verilog?

Re:VHDL or Verilog? by chclau on Monday May 01, 2017 @03:26AM (#14236101)

I don't know ADA, I have always thought that Verilog is like old C and VHDL like C++. Not that VHDL is object oriented, but is a strong-typed language.

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Re:VHDL or Verilog? by oelang on Monday May 01, 2017 @08:16AM (#14236961)

VHDL is an old version of ADA combined with a build-in discrete event simulator. The syntax, type system, general semantics are all copied from ADA.

This is actually a good thing, Verilog (and even more SystemVerilog) is designed by people who don't have a clue about language design resulting in an incredible mess of a language.

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Re:VHDL or Verilog? by beagle3 on Monday May 01, 2017 @05:34AM (#14236439)

VHDL's syntax was borrowed from Ada (and much more closely resembles it than Verilog, which was inspired by C but not adapted from it)

Example Ada: http://perso.telecom-paristech.fr/~pautet/Ada95/e_c16_p5.ada

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Re:VHDL or Verilog? by ajdlinux on Monday May 01, 2017 @04:36AM (#14236285)

VHDL's syntax and type system are quite Ada-ish, from what I gather.

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