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A comment on VHDL or Verilog?. Parent comment

Re:VHDL or Verilog? by beagle3 on Monday May 01, 2017 @05:34AM (#14236439)
VHDL's syntax was borrowed from Ada (and much more closely resembles it than Verilog, which was inspired by C but not adapted from it)

Example Ada: http://perso.telecom-paristech.fr/~pautet/Ada95/e_c16_p5.ada

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