DDR5 memory is on its way, twice as fast as DDR4

Re:DDR5 memory is on its way, twice as fast as DDR4 by jjoonathan on Friday March 31, 2017 @11:02AM (#14004478)

I keep hearing this, but it doesn't jibe with the RAM timings I see. tRAS is usually 50ns or so, and propagation delay is 2ns or so (see below). What gives?

My suspicion is that amplifying the differential voltages produced by femtocoulombs of charge at 100% reliability is a harder problem than moving the DRAM chips closer to the CPU, and that speed-of-light has gotten the blame in "pop architecture" due to sloppy overgeneralization.

    2*2 feet is long for a memory bus, but it's partially cancelled
    out by the high velocity factor (sorry, "speed of electricity")
    of 0.951 in parent's calculations. Instead, I'm going with 0.5*2
    feet at a velocity factor of 0.5 for a 2ns roundtrip propagation delay.

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Re:DDR5 memory is on its way, twice as fast as DDR4 by dfox on Friday March 31, 2017 @12:37PM (#14005495)

Major factor in DRAM latency is in moving these charges around the chip (between the array and sense amplifiers). The wires in the array have some finite conductivity and current handling capability thus this cannot happen instantenuosly.

On the other hand sequential access bandwith is limited almost entirely by the external interface and has more to with economical factors (pin count is major part of IC price) than any physical limitations.

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Re:DDR5 memory is on its way, twice as fast as DDR4 by Retric on Friday March 31, 2017 @11:10AM (#14004576)

https://en.wikipedia.org/wiki/CAS_latency

First word latency: DDR3 SDRAM 6.37ns = 1/156,985,871 of a second.

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Re:DDR5 memory is on its way, twice as fast as DDR4 by jjoonathan on Friday March 31, 2017 @11:11AM (#14004587)

tCL is (very) roughly the RAM equivalent of sequential access time. I'm talking random access time, tRAS, which includes closing the last row (precharging the diff amps) and opening the next (waiting for the amps to stabilize). It's called Random Access Memory, so I think it's more fair to judge it by its random access time.

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Re:DDR5 memory is on its way, twice as fast as DDR4 by Retric on Friday March 31, 2017 @12:20PM (#14005294)

tCL is very much a round trip latency not just sequential access. If you want sequential access 4 times you can pay for tCL once. https://www.altera.com/ja_JP/pdfs/literature/hb/external-mem...

DDR is not really setup for random access, because it's setup for talking to L2/L3 cache not registers. tRAS ~= tCL + tRCD + tRP which kind of but not exactly exactly what you want for random access.

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Re:DDR5 memory is on its way, twice as fast as DDR4 by jjoonathan on Friday March 31, 2017 @08:51PM (#14009680)

Yes, tCL is a round trip time for accessing an already open row, and it puts a sharp upper bound of ~5ns on propagation delay. Random access time, approximated by tRAS, is still ~50ns. You contend that tCL is the bigger problem, I contend that tRAS is the bigger problem. The key statistic is <#CAS/#RAS>, which I haven't been able to find easy values for.

I don't understand your argument that the L2 and L3 caches tip the balance in favor of <#CAS>. If anything, I'd expect them to do the opposite, because the SRAM and DRAM both aim to exploit locality, meaning that better L2 and L3 caches would reduce #CAS faster than #RAS. Of course, armchair reasoning about such complex systems as memory controllers and caches can only go so far, so I wouldn't be shocked to be wrong, but I would certainly demand actual statistics before changing my view.

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