tCL is (very) roughly the RAM equivalent of sequential access time. I'm talking random access time, tRAS, which includes closing the last row (precharging the diff amps) and opening the next (waiting for the amps to stabilize). It's called Random Access Memory, so I think it's more fair to judge it by its random access time.

tCL is very much a round trip latency not just sequential access. If you want sequential access 4 times you can pay for tCL once. https://www.altera.com/ja_JP/pdfs/literature/hb/external-mem...

DDR is not really setup for random access, because it's setup for talking to L2/L3 cache not registers. tRAS ~= tCL + tRCD + tRP which kind of but not exactly exactly what you want for random access.

Yes, tCL is a round trip time for accessing an already open row, and it puts a sharp upper bound of ~5ns on propagation delay. Random access time, approximated by tRAS, is still ~50ns. You contend that tCL is the bigger problem, I contend that tRAS is the bigger problem. The key statistic is <#CAS/#RAS>, which I haven't been able to find easy values for.

I don't understand your argument that the L2 and L3 caches tip the balance in favor of <#CAS>. If anything, I'd expect them to do the opposite, because the SRAM and DRAM both aim to exploit locality, meaning that better L2 and L3 caches would reduce #CAS faster than #RAS. Of course, armchair reasoning about such complex systems as memory controllers and caches can only go so far, so I wouldn't be shocked to be wrong, but I would certainly demand actual statistics before changing my view.