FPGA Acceleration by Dynamically-Loaded Hardware Libraries [pdf]

Re:FPGA Acceleration by Dynamically-Loaded Hardware Librarie... by alain94040 on Sunday October 23, 2016 @10:10PM (#12776415)

What does Clash bring to FPGA design? I can easily imagine how functional languages make it easy to express the datapath of a circuit. But If you still specify registers explictly and have to design your pipeline by hand, it's not a big improvement over traditional HDLs. Can it help you infer correct control logic? That would be useful. Explore different speed/area solutions?

When performance matters - and it does or you wouldn't bother to design hardware - everything gets heavily pipelined with very short logic between pipes stages. Will Clash be any more readable than Verilog then?

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Re:FPGA Acceleration by Dynamically-Loaded Hardware Librarie... by wyager on Monday October 24, 2016 @02:25PM (#12781408)

I think you're focusing on a bit too narrow scope of improvements over traditional HDLs.

A few advantages include: sensible language design, strong types, ADTs, easier and much faster testing/debugging, easier formal verification, easier, more powerful, and safer parametrization, etc.

And yes, even if your clash degenerates to basically copying verilog (which it usually doesn't, in my experience) it's still much easier to read thanks to the richer types and ADTs.

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