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Re:FPGA Acceleration by Dynamically-Loaded Hardware Librarie... by wyager on Monday October 24, 2016 @02:25PM (#12781408)
I think you're focusing on a bit too narrow scope of improvements over traditional HDLs.

A few advantages include: sensible language design, strong types, ADTs, easier and much faster testing/debugging, easier formal verification, easier, more powerful, and safer parametrization, etc.

And yes, even if your clash degenerates to basically copying verilog (which it usually doesn't, in my experience) it's still much easier to read thanks to the richer types and ADTs.

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