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Re:FPGA Acceleration by Dynamically-Loaded Hardware Librarie... by wyager on Sunday October 23, 2016 @05:19PM (#12775478)
I think the single biggest hurdle to FPGA adoption is that FPGA development is horrible. The IDEs suck, everything is license-encumbered and full of DRM, and debugging is a nightmare.

The best thing I've found so far is Clash. It translates Haskell code to (System)Verilog or VHDL. It works remarkably well, and is way easier to write and test than writing VHDL or Verilog directly. You can compile it to a plain old program for testing and debugging, which means you can use things like QuickCheck for aggressive testing. If you're really serious, you can use something like LiquidHaskell for really aggressive formal verification. There's also Lambda-CCC, which looks a bit more theoretically rigorous, but I couldn't get that working when I tried it.

The key here is that non-strict lambda calculus maps remarkably well to hardware, which means that it's actually relatively straightforward to translate a program to an exactly equivalent hardware representation. The only exception is unbounded recursion (at the function or data level), because obviously you can't represent infinite stuff in hardware.

I've written a few FPGA projects using Clash that I never would have had the patience to finish if I had used a traditional HDL. There's usually a bit of a performance hit over hand-optimized HDL, but (as with using e.g. Python over assembly) there are many cases where developer time is more expensive than a small efficiency loss.

Re:FPGA Acceleration by Dynamically-Loaded Hardware Librarie... by alain94040 on Sunday October 23, 2016 @10:10PM (#12776415)
What does Clash bring to FPGA design? I can easily imagine how functional languages make it easy to express the datapath of a circuit. But If you still specify registers explictly and have to design your pipeline by hand, it's not a big improvement over traditional HDLs. Can it help you infer correct control logic? That would be useful. Explore different speed/area solutions?

When performance matters - and it does or you wouldn't bother to design hardware - everything gets heavily pipelined with very short logic between pipes stages. Will Clash be any more readable than Verilog then?

Re:FPGA Acceleration by Dynamically-Loaded Hardware Librarie... by wyager on Monday October 24, 2016 @02:25PM (#12781408)
I think you're focusing on a bit too narrow scope of improvements over traditional HDLs.

A few advantages include: sensible language design, strong types, ADTs, easier and much faster testing/debugging, easier formal verification, easier, more powerful, and safer parametrization, etc.

And yes, even if your clash degenerates to basically copying verilog (which it usually doesn't, in my experience) it's still much easier to read thanks to the richer types and ADTs.

Re:FPGA Acceleration by Dynamically-Loaded Hardware Librarie... by nickpsecurity on Sunday October 23, 2016 @08:53PM (#12776180)
Re:FPGA Acceleration by Dynamically-Loaded Hardware Librarie... by cheiVia0 on Sunday October 23, 2016 @11:22PM (#12776630)
There are open FPGA toolchains now, some links here:

https://wiki.debian.org/FPGA

Re:FPGA Acceleration by Dynamically-Loaded Hardware Librarie... by werdna123 on Sunday October 23, 2016 @05:39PM (#12775563)
I agree. The other big one is power consumption