If you want to get away from that kind of thing, right now I think you're options are POWER8: https://www.raptorengineering.com/TALOS/prerelease.php

AMD has something similar to the Intel Management Engine: https://libreboot.org/faq/#amd

If only I had ~8000 dollars to spend on a desktop I'd be waist-deep in porting Linux packages.

AFAIK IBM's spent a good amount of engineering effort on making linux stuff run on power.

Yes, in practice the only things that really need "porting" to POWER are low-level compilers, languages, runtimes, tooling, etc. that may have arch-specific code. Sometimes IBM does this (e.g. Google v8 + Node.js), sometimes not... yet? (e.g. rust).

There is also this, which is also still pre-release, but looks like it might be a but more affordable.

http://www.lowrisc.org

Not SPARC?

Specifically, the OpenSPARC T2:

http://www.oracle.com/technetwork/systems/opensparc/openspar...

The ASIC implementation was nice:

https://en.wikipedia.org/wiki/UltraSPARC_T2

On a 65nm node... very outdated one... it might get 8 threads in 8 cores at 1.6GHz each with hardware RNG, crypto accelerators, and hypervisor support. That's the kind of implementation that would be useless for an open-source, secure workstation, server, or HPC node. ;) Especially if one slightly increased single-core performance or cache when porting it to 45nm.

Forget that, though. Let's see what IBM will charge for their admittedly-faster pile of complicated silicon that only certain people can see which they've already turned into non-backdoored chips for you. ;)

Sadly the T1/T2 are ancient now. The non-open SPARC is up to T7, which is 20nm process, 256 threads on 32 cores.

Sort of. I run the bloated Web, movies, IDE's, servers, and VM's on a Core Duo with 2 cores under 2GHz done on 65nm. I'd loose some single-threaded performance probably with an OpenSPARC T2 but otherwise it should handle my modern workload. Doesn't quite feel ancient. ;)

The cool thing about open-source CPU's is one can always improve on them to, say, have an extra dozen cores on more recent nodes. Like Oracle does but probably less impressive with less money.

Some anecdata:

Somebody tried to use a university department's T2 because it was unused and reasonably parallel for some experiment on hashing.

Single core SHA1 speed on a t2 was ~300KB/s or so. Even with its 32 threads I recommended going for any ancient desktop that happened not to be used for a couple of days because the experiment would finish much faster there. Those desktops were about Core Duo class and managed 50-100MB/s SHA1 throughput (I think, it's been a couple of years).

What the hell...??? Ok, it's looking like Im going to retract that recommendation for workstations. Maybe still servers thst are I/O bound.

As a 2011 MBA user, I totally understand sticking with old tech that works. T1/T2 isn't really apples-to-apples, though. I came across this random quote from the libgmp devs that made me laugh:

"SPARC chips before T4 under-perform on GMP. This is not because the GMP code is inadequately optimised for SPARC, but due to the basic v9 ISA as well as the micro-architecture of these chips. The T1 and T2 chips perform worse than any other SPARC chips; they compare to a 15 year older 486 chip."

ouch!

Ouch indeed. That's pretty bad. It's believable when I think back to the purpose of these chips: handling workloads that were more I/O and concurrency bound than CPU bound. So, probably identify and eliminate these problems early on even if developer has to drop some threads or cores.

Note: There's always my other recommendation of turning open-source Leon3 into a multicore. Im curious what it or Leon4 get on such a benchmark versus Intels on similar process nodes.

My Rockchip Chromebook doesn't have proprietary microcode, libreboot supported, costs $200. Only proprietary issue is the 3D acceleration

That is the case with many ARM processors. There is a lot of work being made on iGPUs on ARM processors aswell currently such as freedreno, will hopefully be possible to have a good fully open source experience in a few years with arm linux computers.

AMD has it too: https://libreboot.org/faq/#amdpsp

https://libreboot.org/faq/#amd. ARM maybe?

ARM has TrustZone.

TrustZone alone is much closer to a SecureBoot or TPMish feature than ME. It's possible it would allow implementation of an ME-like software stack running inside the TEE.

It's worth mentioning that there is at least one OSS implementation of a TEE software stack, OP-TEE, making this even less of an issue. Assuming your device/soc mfg doesn't lock you out.

http://www.linaro.org/blog/core-dump/op-tee-open-source-secu...

TrustZone is, for practical purposes, a little more open if you're the one designing the board. Most of the time, the crypto is opt in, and you as the final assembler control the keys.