Intel knows it's no longer inside

Re:Intel knows it's no longer inside by cfallin on Wednesday June 01, 2016 @02:16PM (#11816811)

The ALU performs an operation on half of the machine word (16 of the 32 bits) each half-cycle, i.e., one on the rising edge and one on the falling edge of the clock. Basically they split the carry chain across two (half-)pipe stages and then run it twice as fast.

See Hinton et al., "The microarchitecture of the Pentium 4 processor" [1] for all the nifty details -- pp 8-9, and Fig 7 in particular.

[1] http://www.ecs.umass.edu/ece/koren/ece568/papers/Pentium4.pd...

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Re:Intel knows it's no longer inside by userbinator on Wednesday June 01, 2016 @09:15PM (#11819658)

That also makes for some very interesting timings, where the instruction runs faster in the case that there's no carry between the two halves.

From section 2 of this:

https://gmplib.org/~tege/x86-timing.pdf

"Pentium F0-F2 can sustain 3 add r, i per cycle for -32768 <= i <= 32767, but for larger immediate operands it can sustain only about 3/2 per cycle."

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Re:Intel knows it's no longer inside by sirsar on Wednesday June 01, 2016 @02:24PM (#11816876)

Makes sense, thanks!

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